1. Field of the Invention
The present invention relates to multi-channel multiplexing whereby the simultaneous inputs from a plurality of parallel channels may be combined to form a serial output on a single output channel. More particularly, the present invention is a multi-channel CCD multiplexer which utilizes the delay characteristics inherent in the transfer of charges from one CCD electrode to the next electrode to sequentially delay simultaneous inputs which are added at the output to form a serial signal output.
2. Prior Art
In many applications of CCD circuitry, it is necessary to perform high speed multiplexing in conjunction with CCD signal processing schemes. For example, such a function may be necessary for electronically reading out signals from a focal plane or in conjunction with a line-converter memory where data is multiplexed into memory registers and then reassembled using a multiplexer at the output of the registers at data rates on the order of 20 megabits per second. Multiplexing which transfers parallel information from a plurality of channels to serial information on a single channel is presently accomplished by transferring the parallel information into a register and then shifting the information through each register channel to a common output point. In CCD devices of this type, information from a plurality of channels is gated into a CCD register and then the charge on each register is transferred to the next register with the application of appropriate clocking signals until the information is provided at the output from the first channel gate. For example, in a four-channel CCD device, the charge stored in the area of the channel 4 gate is transferred to the channel 3 gate and then to the channel 2 gate and finally to the channel 1 gate before being provided as an output; the charge on the channel 3 gate is transferred to the channel 2 gate and then to the channel 1 gate before being provided as an output; and the charge on the channel 2 gate is transferred to the channel 1 gate before being provided as an output.
Because the amount of charge transferred from one gate to the next depends on the duration of the clock causing the transfer, it is essential in devices where many transfers are required that slow frequency clock signals be utilized to assure high transfer efficiency and to minimize the amount of charge remaining and thereby minimize the amount of "cross-talk" inherently involved due to dispersion in the CCD register. When multiplexing data rates requiring high speed transfers (on the order of 20 megabits per second) are attempted, it is necessary to either decrease the bit length or to limit the number of charge transfers which occur. In addition, most prior art CCD multiplexers require a maximum clock rate equal to the data rate.